1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device. More particularly, the present invention relates to a manufacturing method of a one-time programmable read only memory.
2. Description of the Related Art
With the power of microprocessors continues to expand, the amount of computation in given software programs increases exponentially. As a result, there is an urgent demand for cheap and high storage capacity memories from semiconductor manufacturers. According to the difference in read/write capability, memories can be roughly classified into read only memory (ROM) and random access memory (RAM).
Read only memory is a type of non-volatile data storage device that can retain stored data even when the power is cut off. Hence, most standard electrical products are equipped with some read only memory for holding an initialization program that boots up an operation from the cold.
According to data storage format, read only memory (ROM) can be further sub-divided into mask ROM, one-time programmable ROM, erasable programmable ROM, electrically erasable programmable ROM and so on. Since data can be programmed into a one-time programmable ROM outside the factory according to the particular environment the memory is supposed to be working in, one-time programmable ROM is more convenient to work with than the mask ROM.
A conventional one-time ROM cell includes a diode and an anti-fuse. In general, the presence or the absence of a PN diode linking a word line with a bit line represents the logical value of a stored data bit. Hence, keeping the anti-fuse as it is or breaking open the anti-fuse effectively sets the data value in each memory cell.
For example, in U.S. Pat. No. 6,185,122, a one-time read only memory having vertical stack structure in disclosed. In this patent, a plurality of linear conductive wires is alternately stacked so that the wires cross over each other above a substrate. A diode and an anti-fuse layer are set up between a top conductive wire and a bottom conductive wire in a neighboring pair. The diode and the anti-fuse together form a memory cell. However, in the aforementioned patent, the PN diode is constructed by joining a P-doped polysilicon layer with an N-doped polysilicon layer. Because polysilicon typically includes a large number of grains having a large variation in sizes and many grain boundaries, the properties at the PN junction can hardly be uniform and the leakage pathways can be many. Therefore, a memory device having polysilicon PN diodes may produce memory cells having a wide distribution of properties and a leakage current in the memory cells more readily under a reverse bias voltage.